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Author Topic: DACS: R2R and delta-sigma  (Read 4753 times)

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Stapsy

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DACS: R2R and delta-sigma
« on: December 13, 2013, 02:20:24 AM »

The recent slamming of delta sigma DACs and talk of R2R dacs like the Master 7 and Yggy has got me thinking about how R2R functions.  What is the difference between a chip based ladder DAC like the PCM 1704 in the Master 7 and something like the TotalDac that uses a ton of resistors instead of a chip (I think)?  Are there any inherent advantages and disadvantages of either type? 
« Last Edit: December 13, 2013, 12:45:10 PM by Stapsy »
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thegunner100

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Re: DACS: R2R and delta-sigma
« Reply #1 on: December 13, 2013, 02:46:13 AM »

Could one of you guys explain what sigma delta dacs and r2r dacs are? Theres been a lot of talk, but I have no idea what it all means  :-Z
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Original_Ken

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Re: DACS: R2R and delta-sigma
« Reply #2 on: December 13, 2013, 07:28:39 AM »

Could one of you guys explain what sigma delta dacs and r2r dacs are? Theres been a lot of talk, but I have no idea what it all means  :-Z
You could start with:

http://en.wikipedia.org/wiki/Delta-sigma_modulation
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Marvey

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Re: DACS: R2R and delta-sigma
« Reply #3 on: December 13, 2013, 07:43:22 AM »

For R2R the output level for each sample is determined by the sum of a container of different sizes. For a 5 bit DAC, it would look something like this.

|1|

| |
|2|

|  |
|4_|

|  |
|  |
|  |
|8_|

|    |
|    |
|    |
|_16_|

We can get values from 0-31 this way for a total of 32 values 2^5. The 2 being binary (on or off) and the 5 being the number of bits. The containers need to be accurate, especially once we get to a high number of bits. For example, 20 bits is 2^16 = 65536. Imagine how the accuracy would be thrown off if the largest container were just 1/65536 off. You may as well toss the LSB (smallest container = 1) in the trash.

Anyways, so lets say this 5 bit DAC wants to output a level of 11. The appropriate resistors associated with each container in the DAC would be turned on so the buckets would like this:

|1|

| |
|2|

|  |
|  |
|  |
|8_|

8 plus 2 plus 1 = 11. Makes perfect sense huh?

================================================

For sigma-delta, it's kind of like using a container of the same size (1 bit) and adding or subtracting using only that container. For a 5 bit DAC, this adding and subtracting requires 32 iterations over time. This is why DSD, a one bit format, is specified in zigahertz.

For an output level of 11, this is how the delta-sigma DAC handles it:

01 |1|
02  |0|
03   |0|
04    |1|
05     |0|
06      |0|
07       |0|
08        |1|
09         |0|
10          |0|
11           |1|
12            |0|
13             |0|
14              |1|
15               |0|
16                |0|
17                 |1|
18                  |0|
19                   |0|
20                    |1|
21                     |0|
22                      |0|   
23                       |1|
24                        |0|
25                         |0|
26                          |1|
27                           |0|
28                            |0|
29                             |1|
30                              |0|
31                               |0|
32                                |1|

All this shit added (technically averaged over time) together by being converted via a filter to arrive at the output level of & quot;11". A filter is needed because the process is not simultaneous like the R2R, but rather broken down into iterations over time. The funky thing is how the original sample gets converted from something like an 11 to a series of 1s and 0s with appropriate patterns. Because of this, the output signal is not quite the same, but a good filter does wonders to make it good enough.

The R2R stuff makes perfect sense. The delta-sigma stuff is way more complex. I'll let ultrabike (Changstar's resident DSP/communications engineer, not some phony who keeps reminding us in every other post that he's an engineer) or Jason (a real audio engineer) explain better or correct any mistakes I've made.

It's my understanding that most sigma-delta DACs of today are hybrid R2R / multi-bit systems. DSD is purely one bit.

« Last Edit: December 13, 2013, 08:47:24 AM by purrin »
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ultrabike

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Re: Not a lot of DAC talk on here...
« Reply #4 on: December 13, 2013, 08:33:32 AM »

There are many ways to look at delta-sigma modulation. The simple 1st order (single difference/accumulation stage) single-bit output looks like this:


(reference: http://stuartowen.com/home/2012/08/13/delta-sigma-adc-basics/#!/single_blog)

It's called delta sigma because the operation has a difference (delta) and an accumulator (sigma). In a nutshell, the single bit output of this delta-sigma (DS) tracks the input through difference/accumulation.

1) The DS takes the difference (error) between multi-bit input and the single-bit output (after a gain and delay).

2) The error is then accumulated.

3) Depending on the current error, and previous state of the accumulator, if new accumulator state is greater than zero, then the decision is to output a positive swing. Otherwise one gets a negative swing.

4) The fact that a single bit is being sent out introduces error which is being tracked by both the difference and accumulation operations.

If one was to analyze this whole thing, one would get a pass-through for the signal + a high-pass filtered or "modulated" quantization noise. The quantization noise high-pass filtering operation frequency response (and gain) depends on the "order" of the delta sigma (or how many difference/accumulation stages it has):


(Frequency Response of effective quantization noise high-pass filtering for simple 1st, 2nd and 3rd order delta sigmas. reference from Wikipedia.)

In the end, the output of the delta sigma is low-pass filtered to remove the high-pass quantization. For this to work well, the original signal highest frequency should be well bellow where the quantization noise starts to creep up.

A couple of things to note:

1) A delta sigma can have multiple difference accumulator stages which determines it's order... not just one.
2) The output of the delta sigma does not need to be single bit.
3) Certain "advanced" sigma delta architectures involve feedback and feedforward gains with more than one quantization stage (like multi-stage MASH architectures)
4) Higher order classic delta sigmas are "cleaner" in the pass-band, but put out more garbage in the stop-band. Which makes the subsequent low pass filter's job more difficult.
5) Certain higher order delta sigmas may have stability problems.
6) Classical analysis of delta sigma assumes uniform distributed quantization noise... And in some cases that is a bad assumption.
7) The oversampling rate of the delta sigma (ratio of highest frequency in the signal to the sampling rate) is usually about 8... higher is bettar.

In the end both R2R (Sample/Hold) and delta sigma DACs put out of band poo... and IMO may benefit from "reasonable" analog output filters... which may themselves cause other problems...

Anyhow... for the Matlab inclined here is some quick 1st order ds code:

Code: [Select]
gain = 0.75; % feedback gain
N = 1000; % display samples
delay = 8; % delay alignment
OSR = 8;< span style="white-space: pre;"> % oversampling factor

% signal
[B, A] = butter(7,0.5/OSR);
x=filter(B,A,randn(1,1e5));

% variables
ds = gain*ones(size(x));
diff = zeros(size(x));
acc = zeros(size(x));

% 1st order delta sigma
for i=2:length(x),
diff(i) = x(i) - ds(i-1);
acc(i) = acc(i-1) + diff(i);
ds(i) = gain*(2*(acc(i)>0)-1);
end

% analog output filter
[B, A] = butter(5,1/OSR);
out = filter(B,A,ds);

close all;

% delta sigma input output spectrum
[H, W] = freqz(x);
[Ho, Wo] = freqz(ds);
figure;
subplot(2,1,1);
plot(W,20*log10(abs(H)));
axis tight; grid on;
title('original signal FR mag')
xlabel('radians');
ylabel('au');
subplot(2,1,2);
plot(Wo,20*log10(abs(Ho)));
axis tight; grid on;
title('unfiltered ds output FR mag');
xlabel('radians');
ylabel('au');

% delta sigma output (unfiltered)
figure;
plot(ds(1:N),'.');
axis tight;
grid on;
title('first order delta sigma');
xlabel('sample');
ylabel('units');

% filtered delta sigma output
figure;
plot(x(1:N)); hold on;
plot(out(1+delay:N+delay),'r');
grid on;
axis tight;
title('first order delta sigma');
legend('input','filtered output');

And some results:

Frequency Responses of DS input and unfiltered output



(Note the out-of-band "modulated" quantization noise on sub-plot 2 sort of matches the Wikipedia linky for 1st order)

DS unfiltered output



DS filtered output

« Last Edit: December 13, 2013, 10:34:42 AM by ultrabike »
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Stapsy

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Re: DACS: R2R and delta-sigma
« Reply #5 on: December 13, 2013, 12:38:51 PM »

Here is a discussion of delta-sigma for the layman audiophile that might help as well.  Not nearly as detailed as ultrabike but it was intended for audiophile farts at RMAF  :)p17

http://www.youtube.com/watch?v=1CkyrDIGzOE

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anetode

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Re: DACS: R2R and delta-sigma
« Reply #6 on: December 13, 2013, 03:30:38 PM »

Here are a few excerpts from Pohlmann's Principles of Digital Audio which give a straightforward explanation:
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ultrabike

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Re: DACS: R2R and delta-sigma
« Reply #7 on: December 13, 2013, 05:25:17 PM »

LOL! Here is another way to look at it. Suppose I get a set of integers within a range, and assign to them a unique bit representation... Say:

     5                   -1                  33
00000101 |  11111111 |  00100001

It is clear that the binary representation (2's complement rule) is "faster" or oversampled by 8 relative to it's integer representation. If I had a cheat sheet that showed me how to map bits to these integers, I could go back an forward between representations. I would like the integer representation because it's probably easier for me to understand. On the other hand, the 2's complement binary representation might be easier to deal with for an arithmetic unit inside a computer.

It's sort of a language.

Like in the above example, a low pass filter might be able to "understand" a "fast" binary stream and translate that to suitable analog levels. For example, a set of consecutive 1's might mean "large positive number", and a set of consecutive 0's (or -1's) might mean "large negative number". A set of alternating 1's and 0's (or -1's) might mean "small number" or "zero".

A well designed delta sigma might "translate" and "speak" eloquently in 1's and 0's (or -1's) to a low pass filter that understands this, with sublime results. A poorly designed delta sigma might "speak" binary jive... with not-so sublime results.

Additionally, one could give a set of numbers a different representation using yet another set of smaller magnitude set of numbers (not just 1's and 0's or -1's). The smaller set of numbers would have to be "faster" than the original to keep up, just like the binary representation has to be "faster".

Hope that sort of helps...
« Last Edit: December 13, 2013, 05:43:02 PM by ultrabike »
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Original_Ken

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Re: DACS: R2R and delta-sigma
« Reply #8 on: December 13, 2013, 07:02:39 PM »

I think it is just like album releases:

* An expert transfer from a tape copy of a young original master tape, done in 16/44.1 (Barry Diament 1980s Close to the Edge) easily beats a less expert transfer directly from a now old and worn original master tape at 24/192 (2013 hdtracks and Blu-Rays).

* Similarly, I'm willing to bet that an expert implementation of a delta-sigma with quality parts, beats a less expert r2r implementation with low quality parts and opamp outputs.
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OJneg

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Re: DACS: R2R and delta-sigma
« Reply #9 on: December 13, 2013, 07:42:00 PM »

Great explanations! + 1 for all of you.
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